---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 07:12:57 08/26/2006 -- Design Name: -- Module Name: LoadReg - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- clck - system clock -- btn - board's reset button -- load - module output, loads the shift registers ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity LoadReg is Port ( clk : in std_logic; btn : in std_logic; load : out STD_LOGIC); end LoadReg; architecture One_Shot of LoadReg is BEGIN PROCESS(clk) VARIABLE cntr : INTEGER RANGE 0 to 15000; BEGIN if (clk='1' and clk'Event and cntr < 15000) then cntr := cntr + 1; if (cntr >= 10000 and cntr < 15000) then load <='0'; else load <= '1'; end if; end if; END PROCESS; END One_Shot;